Double data rate (DDR) memory devices can read or write data on both the positive and negative edges (transitions) of a clock signal. Thus, DDR memory provides twice the data rate of memory devices (e.g., SDRAM) that can only read or write data on the positive edge of a clock signal. The main difference between DDR and SDRAM memory is that DDR reads data on both the rising and falling edges of the clock signal. SDRAM only carries information on the rising edge of a signal. This allows the DDR module to transfer data twice as fast as SDRAM. For example, instead of a data rate of 133 MHz, DDR memory transfers data at 266 MHz.
A memory controller may be utilized for interfacing a processor with DDR memory devices. The memory controller supplies write data, a write data strobe, and a write command to a DDR memory with a proper timing relation so that data is reliably written in the memory. During a read operation, the memory controller is further used to fetch data read out from the DDR memory.
During a read operation, as illustrated in FIG. 1, a DDR memory performs the read operation in a well-known manner when a/CS signal goes low and a read command is received. After a time elapses, the DDR memory outputs read data along with a read data strobe signal. And then, a memory controller receives the read data with the read data strobe from the DDR memory. The DDR memory outputs the read data strobe QS coincident with the read data DQs. In other words, the read data strobe QS is coincident with the read data DQs. The read data strobe QS is a signal that is generated in the DDR memory by use of a clock signal CK. One problem, as illustrated in FIG. 1, is that the read data strobe QS is not synchronized with the clock signal CK. The memory controller delays the read data strobe QS by a ¼ clock cycle and fetches data on both positive and negative edges of the delayed read data strobe QS. Accordingly, it is necessary to accurately delay a read data strobe QS by a ¼ clock cycle in the memory controller. Hereinafter, the read data strobe delayed by a ¼ clock cycle is called a ¼ delayed read data strobe.
It is possible to generate the ¼ delayed read data strobe by use of an inverter delay circuit and a delay locked loop (DLL) circuit. A DLL circuit precisely secures a delay time while consuming power over 30 mW. An inverter delay circuit consumes a relatively smaller amount of power while securing the delay time with less precision. This is because a delay time of the inverter delay circuit depends on (manufacturing) process, (power supply) voltage and (circuit) temperature variations, as is illustrated in FIG. 2.
FIG. 2 is a graph that shows the relationship between the number of inverters (connected in series) of three (manufacturing) process types (SS, NN, FF) and a resulting delay time. For example, if an inverter delay circuit consists of 24 inverters fabricated under a process condition of NN, the expected delay time of each the inverter delay circuit will be 1.8 nanoseconds (Nsec, ns).
The label “FF” means that each inverter consists of a fast NMOS transistor and a fast PMOS transistor; “NN” means that an inverter consists of a typical NMOS transistor and a typical PMOS transistor; and “SS” means that an inverter consists of a slow NMOS transistor and a slow PMOS transistor. It is understood from FIG. 2 that a delay time is depends upon the process used to form the inverters in the delay line. For example, a delay time of an inverter delay circuit is relatively longer using inverters made under the SS process condition and relatively shorter using inverters made under the FF process condition. In other words, the delay time of an inverter delay circuit depends upon process variations. This means that it may be difficult to precisely obtain a desired delay time unless the process used to form the inverters is precisely and consistently controlled. Furthermore, as well known by persons skilled in the art, it's the delay time of an inverter delay circuit varies dynamically depending upon variations in temperature and (supply) voltage (PVT).
As a result, it is difficult to generate a precisely specified stable delay signal using an inverter delay circuit.